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74VHC573 Octal D-Type Latch with 3-STATE Outputs
March 1993 Revised May 2005
74VHC573 Octal D-Type Latch with 3-STATE Outputs
General Description
The VHC573 is an advanced high speed CMOS octal latch with 3-STATE output fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This 8-bit D-type latch is controlled by a latch enable input (LE) and an Output Enable input (OE). When the OE input is HIGH, the eight outputs are in a high impedance state. An input protection circuit ensures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages.
Features
s High Speed: tPD
5.0 ns (typ) at VCC VNIL
5V
s High Noise Immunity: VNIH s Low Noise: VOLP
28% VCC (Min)
s Power Down Protection is provided on all inputs
0.6V (typ) 4 PA (Max) @ TA 25qC
s Low Power Dissipation: ICC
s Pin and function compatible with 74HC573
Ordering Code:
Order Number 74VHC573M 74VHC573SJ 74VHC573MTC 74VHC573N Package Number M20B M20D MTC20 N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. Pb-Free package per JEDEC J-STD-020B.
Logic Symbol
IEEE/IEC
Connection Diagram
Pin Descriptions
Pin Names D0-D7 LE OE O0-O7 (c) 2005 Fairchild Semiconductor Corporation Description Data Inputs Latch Enable Input 3-STATE Output Enable Input 3-STATE Outputs
DS011563
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74VHC573
Functional Description
The VHC573 contains eight D-type latches with 3-STATE output buffers. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW the latches store the information that was present on the D inputs, a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are enabled. When OE is HIGH the buffers are in the high impedance mode, but, this does not interfere with entering new data into the latches.
Truth Table
Inputs OE L L L H
H HIGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance
Outputs D H L X X On H L O0 Z
LE H H L X
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74VHC573
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Input Diode Current (IIK) Output Diode Current DC Output Current (IOUT) DC VCC/GND Current (ICC) Storage Temperature (TSTG) Lead Temperature (TL) (Soldering, 10 seconds) 260qC
0.5V to 7.0V 0.5V to 7.0V 0.5V to VCC 0.5V 20 mA r20 mA r25 mA r75 mA 65qC to 150qC
Recommended Operating Conditions (Note 2)
Supply Voltage (VCC) Input Voltage (VIN) Output Voltage (VOUT) Operating Temperature (TOPR) Input Rise and Fall Time (tr, tf) VCC VCC 3.3V r 0.3V 5.0V r 0.5V 0 a 100 ns/V 0 a 20 ns/V 2.0V to 5.5V 0V to 5.5V 0V to VCC
40qC to 85qC
Note 1: Absolute Maximum Ratings are values beyond which the device may be damaged or have its useful life impaired. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside databook specifications. Note 2: Unused inputs must be held HIGH or LOW They may not float.
DC Electrical Characteristics
Symbol VIH VIL VOH Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage VCC (V) 2.0 3.0 5.5 2.0 3.0 5.5 2.0 3.0 4.5 3.0 4.5 VOL LOW Level Output Voltage 2.0 3.0 4.5 3.0 4.5 IOZ IIN ICC 3-STATE Output Off-State Current Input Leakage Current Quiescent Supply Current 0 5.5 5.5 5.5 1.9 2.9 4.4 2.58 3.94 0.0 0.0 0.0 0.1 0.1 0.1 0.36 0.36 2.0 3.0 4.5 TA Min 1.50 0.7 VCC 0.50 0.3 VCC 1.9 2.9 4.4 2.48 3.80 0.1 0.1 0.1 0.44 0.44 V IOL IOL VIN VOUT VIN VIN VIH or VIL VCC or GND 5.5V or GND VCC or GND 4 mA 8 mA V VIN VIH or VIL IOL 50 PA V IOH IOH 25qC Typ Max TA
40qC to 85qC
Max
Min 1.50 0.7 VCC
Units V
Conditions
0.50 0.3 VCC
V V VIN VIH or VIL IOH
50 PA 4 mA 8 mA
r0.25 r0.1
4.0
r2.5 r1.0
40.0
PA PA PA
Noise Characteristics
Symbol VOLP (Note 3) VOLV (Note 3) VIHD (Note 3) VILD (Note 3) Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum HIGH Level Dynamic Input Voltage Maximum LOW Level Dynamic Input Voltage VCC (V) 5.0 5.0 5.0 5.0 TA Typ 0.9 25qC Limits 1.2 Units V V V V CL CL CL CL Conditions 50 pF 50 pF 50 pF 50 pF
0.8
1.0
3.5 1.5
Note 3: Parameter guaranteed by design.
3
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74VHC573
AC Electrical Characteristics
Symbol tPLH tPHL Parameter Propagation Delay Time (LE to On) 5.0 r 0.5 tPLH tPHL Propagation Delay Time (D-On) 3.3 r 0.3 5.0 r 0.5 tPZL tPZH 3-STATE Output Enable Time 3.3 r 0.3 5.0 r 0.5 tPLZ tPHZ tOSLH tOSHL CIN COUT CPD Input Capacitance Output Capacitance Power Dissipation Capacitance
Note 4: Parameter guaranteed by design. tOSLH |tPLH max t PLH min|; tOSHL |tPHL max tPHL min| Note 5: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr.) CPD * VCC * fIN ICC/8 (per Latch). The total C PD when n pcs. of the Latch operates can be calculated by the equation: CPD(total) 21 8n.
VCC (V) 3.3 r 0.3
TA Min
25qC Typ 7.6 10.1 5.0 6.5 7.0 9.5 4.5 6.0 7.3 9.8 5.2 6.7 10.7 6.7 Max 11.9 15.4 7.7 9.7 11.0 14.5 6.8 8.8 11.5 15.0 7.7 9.7 14.5 9.7 1.5 1.0 4 6 29 10
TA
40qC to 85qC
Max 14.0 17.5 9.0 11.0 13.0 16.5 8.0 10.0 13.5 17.0 9.0 11.0 16.5 11.0 1.5 1.0 10 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0
Min
Units ns ns
Conditions CL CL CL CL CL CL CL CL RL 1 k: CL CL CL CL RL 1 k: CL CL (Note 4) VCC VCC Open 5.0V CL CL 15 pF 50 pF 15 pF 50 pF 15 pF 50 pF 15 pF 50 pF 15 pF 50 pF 15 pF 50 pF 50 pF 50 pF 50 pF 50 pF
ns
ns ns ns ns pF pF pF
3-STATE Output Disable Time Output to Output Skew
3.3 r 0.3 5.0 r 0.5 3.3 r 0.3 5.0 r 0.5
(Note 5)
AC Operating Requirements
Symbol tw(H) tw(L) tS tH Minimum Pulse Width (LE) Minimum Setup Time Minimum Hold Time Parameter VCC (V) 3.3 r 0.3 5.0 r 0.5 3.3 r 0.3 5.0 r 0.5 3.3 r 0.3 5.0 r 0.5 TA Min 5.0 5.0 3.5 3.5 1.5 1.5 25qC Typ Max TA
40qC to 85qC
Max 5.0 5.0 3.5 3.5 1.5 1.5
Min
Units ns ns ns
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74VHC573
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B
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74VHC573
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D
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74VHC573
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20
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74VHC573 Octal D-Type Latch with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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